Abstract:
To design a CPU, its instruction set architecture
is first developed, including its instruction set and its
internal registers. A CPU contains three primary
sections: the register section, the ALU, and the
control unit. The micro-operations needed to fetch,
decode, and execute every instruction in its
instruction set are created together with the Register
Transfer Level (RTL) specifications. This paper
proposes a two’s complement multiplier based on the
Robertson's add and shift multiplication algorithm.
The registers and execution units needed to carry out
the micro-operations of the system are designed and
constructed. The computer system generates the RTL
code which specifies the functions to be performed
by the registers and execution units. Based on simple
add and shift operations, with the small amount of
additional logic, multiplication of signed numbers
can be accomplished by the Robertson’s algorithm.
