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Control Unit for MIPS Instruction Using Multicycle Implementation

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dc.contributor.author Zame, Sai Yee
dc.contributor.author Han, Thwe Mu
dc.date.accessioned 2019-08-05T11:18:36Z
dc.date.available 2019-08-05T11:18:36Z
dc.date.issued 2009-12-30
dc.identifier.uri http://onlineresource.ucsy.edu.mm/handle/123456789/1765
dc.description.abstract Architectural advances of modern systems have been added with control complexity, requiring significant effort in both design and verification. The control is the main part of the modern system. In modern system, it has three designs: single-cycle, multicycle and pipelining. In single-cycle, datapath and functional unit can’t be used more than one per instruction because it takes one clock cycle for operation. In multicycle, it executes instruction into multiple steps and each step is executed in one clock cycle. It allows a functional unit to be used more than once per instruction. In pipelining, it is implementation technique in which multiple instructions are overlapped in execution. To have more performance and reduce amount of hardware components, this system uses multicycle. For multicycle operation, control unit generates control signals to datapath elements. So, datapath and control signals for each step of operation are implemented. This system is implemented by verilog language. en_US
dc.language.iso en en_US
dc.publisher Fourth Local Conference on Parallel and Soft Computing en_US
dc.subject multicycle datapath en_US
dc.subject main control en_US
dc.subject ALU control en_US
dc.title Control Unit for MIPS Instruction Using Multicycle Implementation en_US
dc.type Article en_US

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