Abstract:
Pipelining is an implementation technique
whereby multiple instructions are overlapped in
execution; it takes advantage of parallelism that
exits among the actions needed to execute an
instruction. Today, pipelining is the key
implementation technique used to make fast
CPUs. Instructions in the pipeline can depend
on one another, which prevent the next
instruction in the instruction stream from
executing during its designated clock cycle.
Hazards reduce the performance from the ideal
speedup gained by pipelining. This paper will
resolve this problem by using Out-of-Order
execution and register renaming method. In this
design, instructions may be issued out of order
and may be retired out of order as well. The
MIPS microprocessor is used as a running
example to demonstrate our method. In this
paper, it will represent hardware design to be
able to execute out-of-order and the
implementation is simulated by software using
Visual Basic 6.0state-holding elements, called pipeline registers
(delays), into the pipeline. We demonstrate this
process using the MIPS. The MIPS is
decomposed into 5 functional units. They are
Instruction Fetch , Instruction Decode,
Instruction Execution, Memory Access and
Write Back. A functional unit is a portion of the
circuitry that performs a task, which contributes
to the overall objective of processing
instructions.
Pipelining may introduce hazard situations,
which occur when the overlapping of execution
stages of instructions causes incorrect output.
These hazard situations must be detected and
resolved, in order to ensure correct output.
Hazards arise as a result of data dependencies,
instructions that change the pc, and resource
conflicts. There are three types of hazards. They
are structural hazards, data hazards and control hazards.
For a pipeline to process instructions
correctly, hazards must be resolved using
control circuitry (bypass, stall or kill hardware).
The addition of this control circuitry increases
the cost of the stages to which it is added, which
means that pipelining may actually decrease
clock period or instruction throughput, rather
than increase it.