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Implementation of Efficient Radix-4 Butterfly Units for FFT

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dc.contributor.author Aye, Tin Moe
dc.date.accessioned 2019-07-11T06:55:41Z
dc.date.available 2019-07-11T06:55:41Z
dc.date.issued 2013-02-26
dc.identifier.uri http://onlineresource.ucsy.edu.mm/handle/123456789/742
dc.description.abstract Since Fast Fourier Transforms are key components in many of the Digital Signal Processing applications and it is computationally intensive, a software implementation might not meet essential requirements in real time applications where as these vital factors of FFT rely mainly on the butterfly operations. This paper presents the radix 4 butterfly element for Fast Fourier Transform (FFT) processors with sfixed format (signed fixed point) representation and focus on the butterfly design to decrease the computational load of the particular butterflies. As comparing with the typical butterfly unit, the presented butterfly unit reduced the number of complex multiplier units by detaching the latter apart from the former. The proposed system has been developed using hardware description language VHDL on a Xilinx Virtex xc6vlx75t-2ff784 and Virtex xc6vlx75t-3ff484 prototypes and simulated up to the operating frequency of 174.244 MHz as a result of avoiding the trivial multiplications. en_US
dc.language.iso en en_US
dc.publisher Eleventh International Conference On Computer Applications (ICCA 2013) en_US
dc.subject sfixed en_US
dc.subject butterfly en_US
dc.subject FFT en_US
dc.title Implementation of Efficient Radix-4 Butterfly Units for FFT en_US
dc.type Article en_US

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