Design and Implementation of 16 Point Radix 4 Parallel Fast Fourier Transform Processor

dc.contributor.author	Aye, Tin Moe
dc.contributor.author	Zan, Chaw Thet
dc.date.accessioned	2019-07-12T03:34:38Z
dc.date.available	2019-07-12T03:34:38Z
dc.date.issued	2010-12-16
dc.identifier.uri	http://onlineresource.ucsy.edu.mm/handle/123456789/798
dc.description.abstract	The FFT processor is a critical block in all multicarrier systems used primarily in the mobile systems for image and digital signal processing applications. It is therefore interesting to develop an FFT processor as a widely usable VLSI building block. In order to be flexible so that the processor can be used in a variety of applications without major redesign , the performance in terms of computational throughput , and transform length should be: easily modifiable. This system implements the 16 point radix 4 parallel Fast Fourier Transform processor with sfixed format (signed fixed point representation) and focuses on the complex multiplier design with two different approaches.	en_US
dc.language.iso	en	en_US
dc.publisher	Fifth Local Conference on Parallel and Soft Computing	en_US
dc.subject	FFT	en_US
dc.subject	VLSI	en_US
dc.subject	Parallel	en_US
dc.subject	sfixed	en_US
dc.title	Design and Implementation of 16 Point Radix 4 Parallel Fast Fourier Transform Processor	en_US
dc.type	Article	en_US