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Evaluation of Matrix FMA Operation for Array Processor Using Free Cell Library
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| dc.contributor.author | Yuichi, Okuyama
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| dc.contributor.author | Mitsuhiro, Nakamura
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| dc.date.accessioned | 2019-07-03T06:52:23Z | |
| dc.date.available | 2019-07-03T06:52:23Z | |
| dc.date.issued | 2016-02-25 | |
| dc.identifier.uri | http://onlineresource.ucsy.edu.mm/handle/123456789/250 | |
| dc.description | This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. | en_US |
| dc.description.abstract | We implement new arithmetic unit for matrix operation named matrix FMA. This unit read three matrices at one cycle and output the result of 𝐴𝐵+𝐶f in every cycle. We employ this unit to array processor for matrix multiplication and evaluate this unit in 45nm NanGate process. The result shows throughput become double though ×1.3 area penalty in the case of 4×4 matrix operation. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Fourteenth International Conference On Computer Applications (ICCA 2016) | en_US |
| dc.title | Evaluation of Matrix FMA Operation for Array Processor Using Free Cell Library | en_US |
| dc.type | Article | en_US |
