Control Unit for MIPS Instruction Using Multicycle Implementation

Abstract

Architectural advances of modern systems have been added with control complexity, requiring significant effort in both design and verification. The control is the main part of the modern system. In modern system, it has three designs: single-cycle, multicycle and pipelining. In single-cycle, datapath and functional unit can’t be used more than one per instruction because it takes one clock cycle for operation. In multicycle, it executes instruction into multiple steps and each step is executed in one clock cycle. It allows a functional unit to be used more than once per instruction. In pipelining, it is implementation technique in which multiple instructions are overlapped in execution. To have more performance and reduce amount of hardware components, this system uses multicycle. For multicycle operation, control unit generates control signals to datapath elements. So, datapath and control signals for each step of operation are implemented. This system is implemented by verilog language.